FPGAEmu: An Introduction to FPGA Emulation

Note

You can find a brief summary of this project here and don’t forget to check out our GitHub repo.

Important

New to FPGAs or just need a refresher? Jump here first!

Complete Block Diagram of FPGA Board

Hardware Basics

• 1. FPGA Review and Emulation Overview
  • 1.1. A One Minute Introduction to FPGAs
  • 1.2. What is an FPGA anyways?
  • 1.3. What’s Inside an FPGA?
  • 1.4. The Basics of Hardware Emulation and HDLs
  • 1.5. Quick Definitions and Acronyms
  • 1.6. References
• 2. AXI Protocol Overview
  • 2.1. The AXI Protocol
  • 2.2. AXI Reads and Writes
  • 2.3. AXI4 Connections and Channels
  • 2.4. AXI Interconnect vs. SmartConnect
  • 2.5. AXI Verification IP
  • 2.6. References
• 3. Legacy PCI and PCI Express
  • 3.1. Peripheral Component Interconnect
  • 3.2. PCI Overview and Background
  • 3.3. The Legacy PCI Bus Cycle
• 4. DDR Memory and SDRAM
  • 4.1. What is RAM?
  • 4.2. Different Types of RAM
  • 4.3. SRAM
  • 4.4. DRAM
  • 4.5. The DDR SDRAM Protocol
  • 4.6. References
• 5. Clocks, Clocking Wizard, and Timing
  • 5.1. Clocks and Clock Conversion
  • 5.2. Clock Tree
  • 5.3. Multiple Clocks in an FPGA
  • 5.4. Propagation Delay
  • 5.5. Setup and Hold FF Time
  • 5.6. Metastability Prevention
  • 5.7. Clock Domain Crossing (CDC)

Software Basics

• 1. Linux Drivers, Kernel Programming, and You
  • 1.1. What is a Driver?
  • 1.2. Linux Driver Architecture and APIs
  • 1.3. Linux Kernel Modules
  • 1.4. Transferring Data Within the Kernel
  • 1.5. References
• 2. DMA/Bridge for PCIe Drivers Overview
  • 2.1. The PCIe DMA Driver
  • 2.2. Accessing and Building the Xilinx Driver
• 3. Creating a User-Friendly DUT GUI
  • 3.1. What is a GUI?
  • 3.2. System Overview
  • 3.3. Environment Setup

Basic Environment Infrastructure

• 1. MIG 7 Series IP Overview
  • 1.1. Customizing the IP
  • 1.2. Simulating the Example Design
  • 1.3. Simulating Read/Writes with AXI VIP
  • 1.4. Connecting the MIG to a Custom Design
  • 1.5. Connecting the MIG to Two AXI Master VIPs using AXI SmartConnect
• 2. AXI MM to PCIe IP Overview
  • 2.1. Customizing the IP
  • 2.2. Simulating the Example Design
  • 2.3. Example IP Block Diagram
  • 2.4. Replacing the BRAM with DDR MIG in Example Design
  • 2.5. Simulating the AXI MM PCIe MIG Example Design
• 3. DMA/Bridge for PCIe IP Overview
  • 3.1. DMA IP Overview
  • 3.2. The DMA Protocol
  • 3.3. Configuring the DMA IP
  • 3.4. Additional Resources

Device Under Test

• 1. Creating a Custom AXI IP Core
  • 1.1. Packaging Custom IP
  • 1.2. A Simple 8-Bit Counter
  • 1.3. Packaging a Custom AXI4Lite IP
  • 1.4. Adding a Custom AXI IP to a Design
  • 1.5. Creating a Testbench for a Custom DUT
  • 1.6. Interpreting Simulation Waveforms For a Custom DUT
• 2. Creating an Advanced Custom AXI Descriptor IP
  • 2.1. Features of Advanced DUT
  • 2.2. Editing the Descriptor Counter IP
  • 2.3. Creating the Master DUT Simulation Environment
  • 2.4. Testbench for a Master Custom DUT
  • 2.5. Simulating the Master Custom DUT

Emulation Environment

• 1. Building a Basic Simulation Environment (VC707)
  • 1.1. Generating PCIe and MIG Example Designs
  • 1.2. Creating the Block Diagram
  • 1.3. Connecting it All Together
  • 1.4. Modifying and Running the Simulation
  • 1.5. Checking Timing, Viewing Power Reports, Monitoring I/O Placement:
• 2. Building an Emulation Environment (without a Board)
  • 2.1. Project Start (Building the Block Diagram)

Miscellaneous

• 1. Project Summary
  • 1.1. Project Abstract
  • 1.2. Project Background
• 2. Additional Resources
  • 2.1. Tutorials

Indices and tables

• Index

• Search Page

Acknowledgements

FPGAEmu was created and is maintained by a small group of collaborators. Thanks to everyone that has contributed, including:

• Chadmond Wu

• Perry Nesbet

• Haley Guastaferro

• Gabriel Pellot

• Jose Zamudio Gomez

• Ruiwen Wang

• Venkat Shastri, PhD

• Jeffrey Teza

Special thanks to our sponsors that made this all possible: